NXP Semiconductors /MIMXRT1062 /IOMUXC /SW_MUX_CTL_PAD_GPIO_AD_B0_05

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Interpret as SW_MUX_CTL_PAD_GPIO_AD_B0_05

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALT0)MUX_MODE 0 (DISABLED)SION

MUX_MODE=ALT0, SION=DISABLED

Description

SW_MUX_CTL_PAD_GPIO_AD_B0_05 SW MUX Control Register

Fields

MUX_MODE

MUX Mode Select Field.

0 (ALT0): Select mux mode: ALT0 mux port: SRC_BOOT_MODE01 of instance: src

1 (ALT1): Select mux mode: ALT1 mux port: MQS_LEFT of instance: mqs

2 (ALT2): Select mux mode: ALT2 mux port: ENET_TX_DATA02 of instance: enet

3 (ALT3): Select mux mode: ALT3 mux port: SAI2_TX_BCLK of instance: sai2

4 (ALT4): Select mux mode: ALT4 mux port: CSI_DATA08 of instance: csi

5 (ALT5): Select mux mode: ALT5 mux port: GPIO1_IO05 of instance: gpio1

6 (ALT6): Select mux mode: ALT6 mux port: XBAR1_INOUT17 of instance: xbar1

7 (ALT7): Select mux mode: ALT7 mux port: LPSPI3_PCS2 of instance: lpspi3

SION

Software Input On Field.

0 (DISABLED): Input Path is determined by functionality

1 (ENABLED): Force input path of pad GPIO_AD_B0_05

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